This application claims benefit and priority of Korean Patent Application No. 2001-5866, filed on Feb. 7, 2001, under 35 U.S.C. xc2xa7119, the entirety of which is hereby incorporated by reference.
1. Field of the invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a guard ring.
2. Description of Related Art
In a semiconductor memory device, it may be desirable to prevent noise of an external signal from adversely affecting its performance. For example, an external signal may propagate from a terminal to a pad of the semiconductor memory device. If the signal carries a negative undershoot to the pad, the negative undershoot may generate minority carriers, e.g., electrons, in the semiconductor material of the memory device. Such minority carrier noise (e.g., electrons) might then reach and adversely affect memory cells of the memory device.
To avoid such problems, an n-well may be formed in a ring shape surrounding the array of memory cells to serve as guard ring for absorbing minority carriers that may be in the substrate. For example, the guard ring may collect electrons that may be generated by a negative undershoot signal. By collecting such noise electrons, the guard ring prevents the noise electrons from reaching the memory cells of the memory device so that data of the memory cells can remain stable.
Japanese Patent Laid-Open Publication No. hei 6-85203 describes a semiconductor memory device with n-well regions to suppress such noise. The semiconductor memory device includes an I/O circuit region, a periphery circuit region and a memory cell region. In the I/O circuit region, an n-well is formed to surround p-well portions of the I/O circuit region. The n-well of the I/O circuit region is provided a depth deeper than that of the n-well for the periphery circuit region. Similarly, an n-well is formed to surround p-well portions of the memory cell region and is provided a depth deeper than that of the n-wells of the periphery circuit region.
However, for the semiconductor memory device of Japanese Patent Laid-Open Publication No. hei 6-85203, problems may exist with provision of its protective n-wells if the memory cell regions are to become more dense. The n-wells of this memory device may adversely affect an isolation margin (and process margin) between wells of the memory cell region when such designs evolve to higher levels of integration. Accordingly, they can limit the level of integration that might otherwise be available for the memory device.
Additionally, in order to surround the side and bottom portions of the p-wells, the depth of the p-wells is kept less than that of the surrounding n-well. As a result, the push for higher levels of integration will require further reductions in depth for the p-wells, which may affect increased resistance and an increased risk for latch-up. Additionally, the isolation between n+ dopant regions (e.g., source and drain regions of a NMOS transistor) that may be formed in the p-well might also be reduced.
In order to overcome some of the above problems, a semiconductor memory device may have an n-well formed for the periphery circuit region, which will allow for improved levels of integration and enhanced densities for the memory cell region.
FIG. 1 is a simplified plan view illustrating a semiconductor memory device with a guard ring. The semiconductor memory device includes a memory cell region 101 and a periphery circuit region 102. In FIG. 1, the separate memory and periphery regions may be delineated by the one-dot line. Memory cell region 101 includes n-wells 110, p-wells 120 and a plurality of unit cells 141. In FIG. 1, a dotted line delineates the unit cells 141. As shown in this embodiment, the cells may be arranged in a matrix pattern for an array 140. Also, the periphery circuit region 102 may include p-well 125 and n-well 130. N-well 130 may be formed to surround sides of cell array 140 of the memory cell region 101 and may serve as a guard ring to collect electrons that might be generated within the substrate by, e.g., a negative undershoot signal.
In one example, unit cell 141 may comprise an SRAM cell, which may be classified as a full CMOS cell, a high road resistor (HRL) or thin film transistor (TFT) cell as determined in accordance with the type of load. The full CMOS cell, which is more common, uses a bulk PMOS transistor for its load element and comprises two bulk PMOS transistors and four bulk NMOS transistors. Thus, referencing FIG. 1, the memory cell region 101 for the conventional semiconductor memory device may include n-wells 110 for the formation of bulk PMOS transistors and p-well regions 120 for the formation of bulk NMOS transistors.
The n-wells 110, 130 may be formed in respective regions of memory cell region 101 and the periphery circuit region 102, respectively. These n-wells, for the conventional device, are formed at the same time during a single ion implantation process via a common mask. Such exemplary process for manufacturing a semiconductor memory device of FIG. 1, is explained below with reference to FIGS. 2A, 2B, 3A, and 3B. FIGS. 2A and 2B are cross-sectional views taken along line IIxe2x80x94II of FIG. 1, and FIGS. 3A and 3B are cross-sectional views taken along line IIIxe2x80x94III of FIG. 1.
Referring to FIGS. 2A and 3A, a first mask pattern 151 is formed so as to leave exposed portions of, e.g., a p-type semiconductor substrate 100. The exposed portions will correspond to the desired regions for the n-wells. N-type impurities are then ion-implanted into the exposed areas to form n-wells 110 in the memory cell region 101 and n-well 130 in the periphery circuit region 102 as defined by mask pattern 151. As previously described, the regions of n-well 110 may be used to form PMOS transistors in the memory cell region 101, while the regions of n-well 130 may surround the array of cell 140 of the memory cell region 101 to serve as a guard ring. At this point, PMOS transistors may also be formed on the n-well 130 of the periphery circuit region. After forming n-wells 110, 130, the first mask pattern 151 may be removed.
Sequentially, with reference to FIGS. 2B and 3B, a second mask pattern 152 may be formed and patterned to expose portions of the semiconductor substrate 100 where p-wells may be formed. P-type impurities may then be ion-implanted into exposed regions of the substrate to form p-wells 120 in the memory cell region 101 and p-wells 125 in the periphery circuit region 102 as defined by the mask pattern 152. The p-wells 120 of the memory cell region may be located between two neighboring n-wells 110, and the p-wells 125 of the periphery region may be formed on both sides of n-well 130.
As described above, n-well 130 may act as a guard ring to surround a side portion of the memory""s cell array 140 (FIG. 1). But given that n-wells 110 and 130 are formed by the same process step, i.e., through a common one-time ion implantation process that uses a common mask, the n-wells 110 and 130 will have substantially the same depth.
To assist electron collection, the n-well for the guard ring, with reference to the cross-sectional view of FIGS. 4-5, is to effect an electric field through a depletion region and across a PN junction that are formed between the n-well and p-well.
Further referring to FIG. 5, n-well 130 and p-well 125 meet to form a PN junction. A depletion region DR results across the interface of p-well 125 and n-well 130, which may be centered about the PN junction or surface JS. An electric field is formed across the depletion region and may be directed from the n-well 130 toward the p-well 125. Since electrons 126 have a negative polarity, they move in a direction opposite an electric field. Accordingly, electrons 126 may move from regions of p-well 125 to n-well 130 to be collected by the n-well.
Referring to FIG. 4, it is assumed that the substrate 100 comprises, for example, a p-type semiconductor substrate. The region of p-well 125 may comprise p-type dopants of an implant patterned in the periphery region of the semiconductor substrate 100. N-well 130 is formed to surround an array of memory cells of a memory cell region (e.g., 101 of FIG. 1). A PN junction may result between the regions of p-well 125 and n-well 130. Again, a depletion layer results between the p-well 125 and n-well 130 to effect an electric field across the junction.
Electrons 126, 160, respectively, may be generated (e.g., as minority carriers) in p-well 125 and the p-type material of semiconductor substrate 100. These electrons will move toward n-well 130 under the influence of the electric field E associated with depletion region DR. N-well 130, therefore, is able to collect these electrons 126 and 160 and may prevent them from reaching memory cells 141 (FIG. 1) of the memory cell region. N-well 130 thus shields the memory cells 141 from the stray electrons in order to avoid abnormal operations thereof.
It is understood that if n-well 130 can be made larger (i.e., increased width W1 and depth D1 (see FIGS. 2B and 3B)), then the depletion region DR and associated electric field may likewise increase. Accordingly, the larger n-well might then be able to collect more electrons. By collecting more electrons, the n-well would improve noise tolerance by reducing the risk of electrons reaching the memory cell.
However, there may be a limitation to the amount that a width of the n-well guard ring can be increased. When the size of a memory chip is reduced for increasing its level of integration, preferably, all patterns that are associated with the memory chip may be reduced and scaled similarly. Accordingly, the increased levels of integration will call for a reduced width of the n-well that is to act as the guard ring. Therefore, the amount of charge that may be collected by the guard ring would decrease with such higher levels of integration.
To improve the magnitude of an electric field that results from the guard ring might then require an increase for the depth of the n-well associated with the guard ring. However, with n-wells 110, 130 being formed simultaneously in respective memory and periphery regions 101, 102; an increase for the depth of the guard ring would likewise effect a similar increase in depth for the n-wells of the memory cell region. To increase their n-type impurity depths, the n-wells would have to be made with greater ion implantation energy. But such implant energy increase might then adversely affect a process isolation margin. It is understood that a lateral diffusion associated with impurity implants may be proportional to ion implantation energy. Accordingly, a process marginxe2x80x94i.e., for an isolation need between wells in the memory cell regionxe2x80x94might thus be compromised by the greater ion implantation energy. Therefore, there may be a limit to increasing the depth of such guard ring.
Again, as described above, semiconductor memory devices are becoming more highly integrated. With such increase in integration, the width of the n-well 130 that may act as the guard ring will decrease. In order to maintain an electron collection efficiency of the guard ring, there may be a need for increasing its depth. At the same time, it would be nice to be able to increase the depth of the guard ring without compromising process margins. Therefore, as semiconductor devices become more highly integrated, noise suppressing efficiency or electron collection abilities might be affected.
In an exemplary semiconductor memory device having a CMOS type SRAM cell, the memory cell may include two bulk PMOS transistors and four bulk NMOS transistors. PMOS transistors are formed in n-wells and NMOS transistors are formed in the p-wells, which wells may be formed in a memory cell region of the memory device. When an integration level is increased, the cell size is reduced. Accordingly, an isolation between the n-wells and the p-wells may become very important. In other words, an isolation needs to be preserved between the p-type impurity regions of the PMOS transistors that are formed in the n-wells relative to the neighboring p-wells. Also, an isolation need exist for keeping separate the n-type impurity regions of the NMOS transistor in the p-wells relative neighboring n-wells. These isolations can very important for assuring proper SRAM circuit performance. Many attempts have been made to preserve such isolations. For example, some solutions may use an isolation trench, and may provide for an increased depth for these isolation trenches.
Regardless, the formation of highly integrated memory cells of small size may require a process that enables a preservation of an isolation margin between wells as there densities increase. With reduced geometries, the isolation margin may become more sensitive to alignment errorsxe2x80x94i.e., wherein such errors become more pronounced via the reduced geometries. Additionally, an ion implantation process associated with the formation of the wells may adversely affect a lateral diffusion tolerance when trying to form guard rings of sufficient electron collection efficiency. Therefore, the processes associated with ion-implants need to be precisely performed to provide effective guard rings while at the same time controlling implant energy for reduced lateral diffusions.
Exemplary embodiments of the present invention provide for a semiconductor memory device or a method of manufacturing a semiconductor device. Such exemplary embodiments may enable higher levels of device integration and offer improved noise tolerance.
Additionally, exemplary embodiments of the present invention may provide such devices and methods with effective isolation margins.
In accordance with an exemplary embodiment of the present invention, a semiconductor memory device comprises a semiconductor substrate having a memory cell region and a periphery circuit region. The memory cell region may include first and second conductivity type wells and a plurality of memory cells formed on the first and second conductivity type wells. The periphery circuit region may comprises a guard ring adjacent to the second conductivity type well and surrounding a side portion of the memory cell region. The guard ring comprises a depth different from the depth of the second conductivity type well of the memory cell region.
In accordance with another exemplary embodiment, a semiconductor memory device comprises a first conductivity type semiconductor substrate having memory cell and periphery circuit regions. First and second conductivity type wells may be formed on the memory cell region, and an array of memory cells formed on the first and second conductivity type wells. A first conductivity type well may be formed on a portion of the periphery circuit region adjacent the memory cell region. A well of the second conductivity may be formed adjacent to the well of the first conductivity type in the periphery circuit region and surrounding a side portion of the memory cell region. Additionally, it will have a depth deeper depth than the second conductivity type well of the memory cell region.
In accordance with still a further embodiment of the present invention, a semiconductor memory device comprises a semiconductor substrate having memory and periphery regions. A first conductivity type well may be formed in the memory cell region. A guard ring is formed in the periphery circuit region to surround a side portion of the memory cell region and with a depth different from that of the first conductivity-type well.
In another exemplary embodiment of the present invention, a semiconductor memory device comprises a first conductivity type semiconductor substrate. Wells of a first conductivity type are formed in memory and periphery circuit regions of the semiconductor substrate. A well of a second conductivity type is formed in the periphery circuit region surrounding a side portion of the memory cell region. The second conductivity type well is formed with a depth deeper than that of the first conductivity-type well in the memory cell region.
The present invention further provides for a method of manufacturing a semiconductor memory device. A first mask pattern is formed on a semiconductor substrate with openings to expose select regions of the substrate. Impurities of a first conductivity type may then be implanted with a first ion implantation energy into the select regions of the semiconductor substrate to form wells of the first conductivity type therein as defined by the first mask pattern. A second mask pattern may be formed over the semiconductor, and further impurities of the first conductivity type implanted with a second ion implantation energy into a select area of the periphery circuit region of the semiconductor substrate as defined by the second mask pattern. In this embodiment, the second ion implantation energy is greater than the first ion implantation energy. This method may further comprise forming a third mask pattern over the semiconductor substrate to expose portions thereof other than those of the first conductivity type wells. Second conductivity type impurities may then be implanted into areas of the semiconductor substrate as defined by the third mask pattern and second conductivity type wells formed in the memory cell and the periphery circuit regions of the semiconductor substrate.
In accordance with another embodiment of the present invention, a method of manufacturing a semiconductor memory device comprises forming a first mask pattern on a semiconductor substrate to expose a portion of a periphery circuit region thereof. Using a first ion implantation energy, impurities of a first conductivity type are implanted into regions of the semiconductor substrate defined by the first mask pattern to provide for the formation of a first conductivity type well in the periphery circuit region. A second mask pattern may then be formed over the semiconductor substrate to expose at least a portion of the first conductivity type well in the periphery circuit region and a portion of the memory cell region. Using a second ion implantation energy, additional impurities of the first conductivity type may then be implanted into areas of the semiconductor substrate defined by the second mask pattern to assist formation, or further formation, of first conductivity type wells in the memory cell and periphery circuit regions. In this embodiment, the magnitude of the second ion implementation energy is less than that of the first ion implantation energy. A third mask pattern may be formed on the semiconductor substrate to expose at least portions of the semiconductor substrate other than those for the first conductivity type wells. Impurities of a second conductivity type may then be implanted into regions of the semiconductor substrate defined by the third mask pattern to provide for the formation of second conductivity type wells in the memory cell and the periphery circuit regions of the semiconductor substrate.
In accordance with further exemplary embodiments, the semiconductor substrate may be prepared with a conductivity type that is the same as that of the first conductivity type well, and the guard ring may comprise material of the second conductivity type. For example, the semiconductor substrate may comprise a p-type semiconductor substrate and the guard ring may comprise an n-well. Additionally, the guard ring comprises a depth deeper than that of the second conductivity type well of the memory cell region. For example, the guard ring may comprise a depth that is at least 0.1 xcexcm as deep as the second conductivity type well in the memory cell region. In further exemplary embodiments, the cells of the memory cell region comprise DRAM cells.